Z80 Instruction Set

8 Bit Transfer Instructions
Z80 Mnemonic Machine Code Operation
LD A,A 7F A ← A
LD A,B 78 A ← B
LD A,C 79 A ← C
LD A,D 7A A ← D
LD A,E 7B A ← E
LD A,H 7C A ← H
LD A,L 7D A ← L
LD A,(HL) 7E A ← (HL)
LD A,(BC) 0A A ← (BC)
LD A,(DE) 1A A ← (DE)
LD A,(word) 3Aword A ← (word)
LD A,(IX+index) DD7Eindex A ← (IX+index)
LD A,(IY+index) FD7Eindex A ← (IY+index)
LD B,A 47 B ← A
LD B,B 40 B ← B
LD B,C 41 B ← C
LD B,D 42 B ← D
LD B,E 43 B ← E
LD B,H 44 B ← H
LD B,L 45 B ← L
LD B,(HL) 46 B ← (HL)
LD B,(IX+index) DD46index B ← (IX+index)
LD B,(IY+index) FD46index B ← (IY+index)
LD C,A 4F C ← A
LD C,B 48 C ← B
LD C,C 49 C ← C
LD C,D 4A C ← D
LD C,E 4B C ← E
LD C,H 4C C ← H
LD C,L 4D C ← L
LD C,(HL) 4E C ← (HL)
LD C,(IX+index) DD4Eindex C ← (IX+index)
LD C,(IY+index) FD4Eindex C ← (IY+index)
LD D,A 57 D ← A
LD D,B 50 D ← B
LD D,C 51 D ← C
LD D,D 52 D ← D
LD D,E 53 D ← E
LD D,H 54 D ← H
LD D,L 55 D ← L
LD D,(HL) 56 D ← (HL)
LD D,(IX+index) DD56index D ← (IX+index)
LD D,(IY+index) FD56index D ← (IY+index)
LD E,A 5F E ← A
LD E,B 58 E ← B
LD E,C 59 E ← C
LD E,D 5A E ← D
LD E,E 5B E ← E
LD E,H 5C E ← H
LD E,L 5D E ← L
LD E,(HL) 5E E ← (HL)
LD E,(IX+index) DD5Eindex E ← (IX+index)
LD E,(IY+index) FD5Eindex E ← (IY+index)
LD H,A 67 H ← A
LD H,B 60 H ← B
LD H,C 61 H ← C
LD H,D 62 H ← D
LD H,E 63 H ← E
LD H,H 64 H ← H
LD H,L 65 H ← L
LD H,(HL) 66 H ← (HL)
LD H,(IX+index) DD66index H ← (IX+index)
LD H,(IY+index) FD66index H ← (IY+index)
LD L,A 6F L ← A
LD L,B 68 L ← B
LD L,C 69 L ← C
LD L,D 6A L ← D
LD L,E 6B L ← E
LD L,H 6C L ← H
LD L,L 6D L ← L
LD L,(HL) 6E L ← (HL)
LD L,(IX+index) DD6Eindex L ← (IX+index)
LD L,(IY+index) FD6Eindex L ← (IY+index)
LD (HL),A 77 (HL) ← A
LD (HL),B 70 (HL) ← B
LD (HL),C 71 (HL) ← C
LD (HL),D 72 (HL) ← D
LD (HL),E 73 (HL) ← E
LD (HL),H 74 (HL) ← H
LD (HL),L 75 (HL) ← L
LD (IX+index),A DD77index (IX+index) ← A
LD (IX+index),B DD70index (IX+index) ← B
LD (IX+index),C DD71index (IX+index) ← C
LD (IX+index),D DD72index (IX+index) ← D
LD (IX+index),E DD73index (IX+index) ← E
LD (IX+index),H DD74index (IX+index) ← H
LD (IX+index),L DD75index (IX+index) ← L
LD (IX+index),byte DD76indexbyte (IX+index) ← byte
LD (IY+index),A FD77index (IY+index) ← A
LD (IY+index),B FD70index (IY+index) ← B
LD (IY+index),C FD71index (IY+index) ← C
LD (IY+index),D FD72index (IY+index) ← D
LD (IY+index),E FD73index (IY+index) ← E
LD (IY+index),H FD74index (IY+index) ← H
LD (IY+index),L FD75index (IY+index) ← L
LD (IY+index),byte FD76indexbyte (IY+index) ← byte
LD A,byte 3Ebyte A ← byte
LD B,byte 06byte B ← byte
LD C,byte 0Ebyte C ← byte
LD D,byte 16byte D ← byte
LD E,byte 1Ebyte E ← byte
LD H,byte 26byte H ← byte
LD L,byte 2Ebyte L ← byte
LD (HL),byte 36byte (HL) ← byte
LD (IX+index),byte DD36index byte (IX+index) ← byte
LD (IY+index),byte FD36index byte (IY+index) ← byte
LD (BC),A 02 (BC) ← A
LD (DE),A 12 (DE) ← A
LD (word),A 32word (word) ← A

16 Bit Transfer Instructions
Z80 Mnemonic Machine Code Operation
LD BC,word 01word BC ← word
LD DE,word 11word DE ← word
LD HL,word 21word HL ← word
LD SP,word 31word SP ← word
LD IX,word DD21word IX ← word
LD IY,word FD21word IY ← word
LD HL,(word) 2Aword HL ← (word)
LD BC,(word) ED4Bword BC ← (word)
LD DE,(word) ED5Bword DE ← (word)
LD HL,(word) ED6Bword HL ← (word)
LD SP,(word) ED7Bword SP ← (word)
LD IX,(word) DD2Aword IX ← (word)
LD IY,(word) FD2Aword IY ← (word)
LD (word),HL 22word (word) ← HL
LD (word),BC ED43word (word) ← BC
LD (word),DE ED53word (word) ← DE
LD (word),HL ED6Bword (word) ← HL
LD (word),IX DD22word (word) ← IX
LD (word),IY FD22word (word) ← IY
LD (word),SP ED73word (word) ← SP
LD SP,HL F9 SP ← HL
LD SP,IX DDF9 SP ← IX
LD SP,IY FDF9 SP ← IY

Register Exchange Instructions
Z80 Mnemonic Machine Code Operation
EX DE,HL EB HL ↔ DE
EX (SP),HL E3 H ↔ (SP+1); L ↔ (SP)
EX (SP),IX DDE3 IXh ↔ (SP+1); IXl ↔ (SP)
EX (SP),IY FDE3 IYh ↔ (SP+1); IYl ↔ (SP)
EX AF,AF' 08 AF ↔ AF'
EXX D9 BC/DE/HL ↔ BC'/DE'/HL'

Add Byte Instructions
Z80 Mnemonic Machine Code Operation
ADD A,A 87 A ← A+A
ADD A,B 80 A ← A+B
ADD A,C 81 A ← A+C
ADD A,D 82 A ← A+D
ADD A,E 83 A ← A+E
ADD A,H 84 A ← A+H
ADD A,L 85 A ← A+L
ADD A,(HL) 86 A ← A+(HL)
ADD A,(IX+index) DD86index A ← A+(IX+index)
ADD A,(IY+index) FD86index A ← A+(IY+index)
ADD A,byte C6byte A ← A+byte

Add Byte with Carry-In Instructions
Z80 Mnemonic Machine Code Operation
ADC A,A 8F A ← A+A+Carry
ADC A,B 88 A ← A+B+Carry
ADC A,C 89 A ← A+C+Carry
ADC A,D 8A A ← A+D+Carry
ADC A,E 8B A ← A+E+Carry
ADC A,H 8C A ← A+H+Carry
ADC A,L 8D A ← A+L+Carry
ADC A,(HL) 8E A ← A+(HL)+Carry
ADC A,(IX+index) DD8Eindex A ← A+(IX+index)+Carry
ADC A,(IY+index) FD8Eindex A ← A+(IY+index)+Carry
ADC A,byte CEbyte A ← A+byte+Carry

Subtract Byte Instructions
Z80 Mnemonic Machine Code Operation
SUB A 97 A ← A−A
SUB B 90 A ← A−B
SUB C 91 A ← A−C
SUB D 92 A ← A−D
SUB E 93 A ← A−E
SUB H 94 A ← A−H
SUB L 95 A ← A−L
SUB (HL) 96 A ← A−(HL)
SUB (IX+index) DD96index A ← A−(IX+index)
SUB (IY+index) FD96index A ← A−(IY+index)
SUB byte D6byte A ← A−byte

Subtract Byte With Borrow-In Instructions
Z80 Mnemonic Machine Code Operation
SBC A 9F A ← A−A−Carry
SBC B 98 A ← A−B−Carry
SBC C 99 A ← A−C−Carry
SBC D 9A A ← A−D−Carry
SBC E 9B A ← A−E−Carry
SBC H 9C A ← A−H−Carry
SBC L 9D A ← A−L−Carry
SBC (HL) 9E A ← A−(HL)−Carry
SBC (IX+index) DD9Eindex A ← A−(IX+index)−Carry
SBC (IY+index) FD9Eindex A ← A−(IY+index)−Carry
SBC byte DEbyte A ← A−byte−Carry

Double Byte Add Instructions
Z80 Mnemonic Machine Code Operation
ADD HL,BC 09 HL ← HL+BC
ADD HL,DE 19 HL ← HL+DE
ADD HL,HL 29 HL ← HL+HL
ADD HL,SP 39 HL ← HL+SP
ADD IX,BC DD09 IX ← IX+BC
ADD IX,DE DD19 IX ← IX+DE
ADD IX,IX DD29 IX ← IX+IX
ADD IX,SP DD39 IX ← IX+SP
ADD IY,BC FD09 IY ← IY+BC
ADD IY,DE FD19 IY ← IY+DE
ADD IY,IY FD29 IY ← IY+IY
ADD IY,SP FD39 IY ← IY+SP

Double Byte Add With Carry-In Instructions
Z80 Mnemonic Machine Code Operation
ADC HL,BC ED4A HL ← HL+BC+Carry
ADC HL,DE ED5A HL ← HL+DE+Carry
ADC HL,HL ED6A HL ← HL+HL+Carry
ADC HL,SP ED7A HL ← HL+SP+Carry

Double Byte Subtract With Borrow-In Instructions
Z80 Mnemonic Machine Code Operation
SBC HL,BC ED42 HL ← HL−BC−Carry
SBC HL,DE ED52 HL ← HL−DE−Carry
SBC HL,HL ED62 HL ← HL−HL−Carry
SBC HL,SP ED72 HL ← HL−SP−Carry

Control Instructions
Z80 Mnemonic Machine Code Operation
DI F3 IFF ← 0
EI FB IFF ← 1
IM 0 ED46
IM 1 ED56
IM 2 ED5E
LD A,I ED57 A ← Interrupt Page
LD I,A ED47 Interrupt Page ← A
LD A,R ED5F A ← Refresh Register
LD R,A ED4F Refresh Register ← A
NOP 00 No Operation
HLT 76 NOP;PC ← PC-1

Increment Byte Instructions
Z80 Mnemonic Machine Code Operation
INC A 3C A ← A+1
INC B 04 B ← B+1
INC C 0C C ← C+1
INC D 14 D ← D+1
INC E 1C E ← E+1
INC H 24 H ← H+1
INC L 2C L ← L+1
INC (HL) 34 (HL) ← (HL)+1
INC (IX+index) DD34index (IX+index) ← (IX+index)+1
INC (IY+index) FD34index (IY+index) ← (IY+index)+1

Decrement Byte Instructions
Z80 Mnemonic Machine Code Operation
DEC A 3D A ← A−1
DEC B 05 B ← B−1
DEC C 0D C ← C−1
DEC D 15 D ← D−1
DEC E 1D E ← E−1
DEC H 25 H ← H−1
DEC L 2D L ← L−1
DEC (HL) 35 (HL) ← (HL)−1
DEC (IX+index) DD35index (IX+index) ← (IX+index)−1
DEC (IY+index) FD35index (IY+index) ← (IY+index)−1

Increment Register Pair Instructions
Z80 Mnemonic Machine Code Operation
INC BC 03 BC ← BC+1
INC DE 13 DE ← DE+1
INC HL 23 HL ← HL+1
INC SP 33 SP ← SP+1
INC IX DD23 IX ← IX+1
INC IY FD23 IY ← IY+1

Decrement Register Pair Instructions
Z80 Mnemonic Machine Code Operation
DEC BC 0B BC ← BC−1
DEC DE 1B DE ← DE−1
DEC HL 2B HL ← HL−1
DEC SP 3B SP ← SP−1
DEC IX DD2B IX ← IX−1
DEC IY FD2B IY ← IY−1

Special Accumulator and Flag Instructions
Z80 Mnemonic Machine Code Operation
DAA 27
CPL 2F A ← NOT A
SCF 37 CF (Carry Flag) ← 1
CCF 3F CF (Carry Flag) ← NOT CF
NEG ED44 A ← 0−A

Rotate Instructions
Z80 Mnemonic Machine Code Operation
RLCA 07
RRCA 0F
RLA 17
RRA 1F
RLD ED6F
RRD ED67
RLC A CB07
RLC B CB00
RLC C CB01
RLC D CB02
RLC E CB03
RLC H CB04
RLC L CB05
RLC (HL) CB06
RLC (IX+index) DDCBindex06
RLC (IY+index) FDCBindex06
RL A CB17
RL B CB10
RL C CB11
RL D CB12
RL E CB13
RL H CB14
RL L CB15
RL (HL) CB16
RL (IX+index) DDCBindex16
RL (IY+index) FDCBindex16
RRC A CB0F
RRC B CB08
RRC C CB09
RRC D CB0A
RRC E CB0B
RRC H CB0C
RRC L CB0D
RRC (HL) CB0E
RRC (IX+index) DDCBindex0E
RRC (IY+index) FDCBindex0E
RR A CB1F
RR B CB18
RR C CB19
RR D CB1A
RR E CB1B
RR H CB1C
RR L CB1D
RR (HL) CB1E
RR (IX+index) DDCBindex1E
RR (IY+index) FDCBindex1E

Logical Byte Instructions
Z80 Mnemonic Machine Code Operation
AND A A7 A ← A AND A
AND B A0 A ← A AND B
AND C A1 A ← A AND C
AND D A2 A ← A AND D
AND E A3 A ← A AND E
AND H A4 A ← A AND H
AND L A5 A ← A AND L
AND (HL) A6 A ← A AND (HL)
AND (IX+index) DDA6index A ← A AND (IX+index)
AND (IY+index) FDA6index A ← A AND (IY+index)
AND byte E6byte A ← A AND byte
XOR A AF A ← A XOR A
XOR B A8 A ← A XOR B
XOR C A9 A ← A XOR C
XOR D AA A ← A XOR D
XOR E AB A ← A XOR E
XOR H AC A ← A XOR H
XOR L AD A ← A XOR L
XOR (HL) AE A ← A XOR (HL)
XOR (IX+index) DDAEindex A ← A XOR (IX+index)
XOR (IY+index) FDAEindex A ← A XOR (IY+index)
XOR byte EEbyte A ← A XOR byte
OR A B7 A ← A OR A
OR B B0 A ← A OR B
OR C B1 A ← A OR C
OR D B2 A ← A OR D
OR E B3 A ← A OR E
OR H B4 A ← A OR H
OR L B5 A ← A OR L
OR (HL) B6 A ← A OR (HL)
OR (IX+index) DDB6index A ← A OR (IX+index)
OR (IY+index) FDB6index A ← A OR (IY+index)
OR byte F6byte A ← A OR byte
CP A BF A−A
CP B B8 A−B
CP C B9 A−C
CP D BA A−D
CP E BB A−E
CP H BC A−H
CP L BD A−L
CP (HL) BE A−(HL)
CP (IX+index) DDBEindex A−(IX+index)
CP (IY+index) FDBEindex A−(IY+index)
CP byte FEbyte A−byte
CPI EDA1 A−(HL);HL ← HL+1;BC ← BC-1
CPIR EDB1 A−(HL);HL ← HL+1;BC ← BC-1
CPD EDA9 A−(HL);HL ← HL−1;BC ← BC-1
CPDR EDB9 A−(HL);HL ← HL−1;BC ← BC-1

Branch Control/Program Counter Load Instructions
Z80 Mnemonic Machine Code Operation
JP address C3address PC ← address
JP NZ,address C2address If NZ, PC ← address
JP Z,address CAaddress If Z, PC ← address
JP NC,address D2address If NC, PC ← address
JP C,address DAaddress If C, PC ← address
JP PO,address E2address If PO, PC ← address
JP PE,address EAaddress If PE, PC ← address
JP P,address F2address If P, PC ← address
JP M,address FAaddress If M, PC ← address
JP (HL) E9 PC ← HL
JP (IX) DDE9 PC ← IX
JP (IY) FDE9 PC ← IY
JR index 18index PC ← PC+index
JR NZ,index 20index If NZ, PC ← PC+index
JR Z,index 28index If Z, PC ← PC+index
JR NC,index 30index If NC, PC ← PC+index
JR C,index 38index If C, PC ← PC+index
DJNZ index 10index B ← B−1; while B > 0, PC ← PC+index
CALL address CDaddress (SP-1) ← PCh;(SP-2) ← PCl; SP ← SP−2;PC ← address
CALL NZ,address C4address If NZ, CALL address
CALL Z,address CCaddress If Z, CALL address
CALL NC,address D4address If NC, CALL address
CALL C,address DCaddress If C, CALL address
CALL PO,address E4address If PO, CALL address
CALL PE,address ECaddress If PE, CALL address
CALL P,address F4address If P, CALL address
CALL M,address FCaddress If M, CALL address
RET C9 PCl ← (SP);PCh ← (SP+1); SP ← (SP+2)
RET NZ C0 If NZ, RET
RET Z C8 If Z, RET
RET NC D0 If NC, RET
RET C D8 If C, RET
RET PO E0 If PO, RET
RET PE E8 If PE, RET
RET P F0 If P, RET
RET M F8 If M, RET
RETI ED4D Return from Interrupt
RETN ED45 IFF1 ← IFF2;RETI
RST 0 C7 CALL 0
RST 8 CF CALL 8
RST 10H D7 CALL 10H
RST 18H DF CALL 18H
RST 20H E7 CALL 20H
RST 28H EF CALL 28H
RST 30H F7 CALL 30H
RST 38H FF CALL 38H

Stack Operation Instructions
Z80 Mnemonic Machine Code Operation
PUSH BC C5 (SP−2) ← C; (SP−1) ← B; SP ← SP−2
PUSH DE D5 (SP−2) ← E; (SP−1) ← D; SP ← SP−2
PUSH HL E5 (SP−2) ← L; (SP−1) ← H; SP ← SP−2
PUSH AF F5 (SP−2) ← Flags; (SP−1) ← A; SP ← SP−2
PUSH IX DDE5 (SP−2) ← IXl; (SP−1) ← IXh; SP ← SP−2
PUSH IY FDE5 (SP−2) ← IYl; (SP−1) ← IYh; SP ← SP−2
POP BC C1 B ← (SP+1); C ← (SP); SP ← SP+2
POP DE D1 D ← (SP+1); E ← (SP); SP ← SP+2
POP HL E1 H ← (SP+1); L ← (SP); SP ← SP+2
POP AF F1 A ← (SP+1); Flags ← (SP); SP ← SP+2
POP IX DDE1 IXh ← (SP+1); IXl ← (SP); SP ← (SP+2)
POP IY FDE1 IYh ← (SP+1); IYl ← (SP); SP <= (SP+2)

Input/Output Instructions
Z80 Mnemonic Machine Code Operation
IN A,(byte) DBbyte A ← [byte]
IN A,(C) ED78 A ← [C]
IN B,(C) ED40 B ← [C]
IN C,(C) ED48 C ← [C]
IN D,(C) ED50 D ← [C]
IN E,(C) ED58 E ← [C]
IN H,(C) ED60 H ← [C]
IN L,(C) ED68 L ← [C]
INI EDA2 (HL) ← [C];B ← B−1;HL ← HL+1
INIR EDB2 (HL) ← [C];B ← B−1;HL ← HL+1; Repeat while B>0
IND EDAA (HL) ← [C];B ← B−1;HL ← HL−1
INDR EDBA (HL) ← [C];B ← B−1;HL ← HL−1; Repeat while B>0
OUT (byte),A D3byte [byte] ← A
OUT (C),A ED79 [C] ← A
OUT (C),B ED41 [C] ← B
OUT (C),C ED49 [C] ← C
OUT (C),D ED51 [C] ← D
OUT (C),E ED59 [C] ← E
OUT (C),H ED61 [C] ← H
OUT (C),L ED69 [C] ← L
OUTI EDA3 [C] ← (HL);B ← B−1;HL ← HL+1
OTIR EDB3 [C] ← (HL);B ← B−1;HL ← HL+1; Repeat while B>0
OUTD EDAB [C] ← (HL);B ← B−1;HL ← HL−1
OTDR EDBB [C] ← (HL);B ← B−1;HL ← HL−1; Repeat while B>0

Data Transfer Instructions
Z80 Mnemonic Machine Code Operation
LDI EDA0 (DE) ← (HL);HL ← HL+1; DE ← DE+1; BC ← BC−1
LDIR EDB0 (DE) ← (HL);HL ← HL+1; DE ← DE+1; BC ← BC−1; repeat while BC≠-1
LDD EDA8 (DE) ← (HL);HL ← HL−1; DE ← DE-1; BC ← BC−1
LDDR EDB8 (DE) ← (HL);HL ← HL−1; DE ← DE−1; BC ← BC−1; repeat while BC≠-1

Bit Manipulation Instructions
Z80 Mnemonic Machine Code Operation
BIT 0,A CB47 Z flag ← NOT Bit 0
BIT 0,B CB40 Z flag ← NOT Bit 0
BIT 0,C CB41 Z flag ← NOT Bit 0
BIT 0,D CB42 Z flag ← NOT Bit 0
BIT 0,E CB43 Z flag ← NOT Bit 0
BIT 0,H CB44 Z flag ← NOT Bit 0
BIT 0,L CB45 Z flag ← NOT Bit 0
BIT 0,(HL) CB46 Z flag ← NOT Bit 0
BIT 0,(IX+index) DDCBindex46 Z flag ← NOT Bit 0
BIT 0,(IY+index) FDCBindex46 Z flag ← NOT Bit 0
BIT 1,A CB4F Z flag ← NOT Bit 1
BIT 1,B CB48 Z flag ← NOT Bit 1
BIT 1,C CB49 Z flag ← NOT Bit 1
BIT 1,D CB4A Z flag ← NOT Bit 1
BIT 1,E CB4B Z flag ← NOT Bit 1
BIT 1,H CB4C Z flag ← NOT Bit 1
BIT 1,L CB4D Z flag ← NOT Bit 1
BIT 1,(HL) CB4E Z flag ← NOT Bit 1
BIT 1,(IX+index) DDCBindex4E Z flag ← NOT Bit 1
BIT 1,(IY+index) FDCBindex4E Z flag ← NOT Bit 1
BIT 2,A CB57 Z flag ← NOT Bit 2
BIT 2,B CB50 Z flag ← NOT Bit 2
BIT 2,C CB51 Z flag ← NOT Bit 2
BIT 2,D CB52 Z flag ← NOT Bit 2
BIT 2,E CB53 Z flag ← NOT Bit 2
BIT 2,H CB54 Z flag ← NOT Bit 2
BIT 2,L CB55 Z flag ← NOT Bit 2
BIT 2,(HL) CB56 Z flag ← NOT Bit 2
BIT 2,(IX+index) DDCBindex56 Z flag ← NOT Bit 2
BIT 2,(IY+index) FDCBindex56 Z flag ← NOT Bit 2
BIT 3,A CB5F Z flag ← NOT Bit 3
BIT 3,B CB58 Z flag ← NOT Bit 3
BIT 3,C CB59 Z flag ← NOT Bit 3
BIT 3,D CB5A Z flag ← NOT Bit 3
BIT 3,E CB5B Z flag ← NOT Bit 3
BIT 3,H CB5C Z flag ← NOT Bit 3
BIT 3,L CB5D Z flag ← NOT Bit 3
BIT 3,(HL) CB5E Z flag ← NOT Bit 3
BIT 3,(IX+index) DDCBindex5E Z flag ← NOT Bit 3
BIT 3,(IY+index) FDCBindex5E Z flag ← NOT Bit 3
BIT 4,A CB67 Z flag ← NOT Bit 4
BIT 4,B CB60 Z flag ← NOT Bit 4
BIT 4,C CB61 Z flag ← NOT Bit 4
BIT 4,D CB62 Z flag ← NOT Bit 4
BIT 4,E CB63 Z flag ← NOT Bit 4
BIT 4,H CB64 Z flag ← NOT Bit 4
BIT 4,L CB65 Z flag ← NOT Bit 4
BIT 4,(HL) CB66 Z flag ← NOT Bit 4
BIT 4,(IX+index) DDCBindex66 Z flag ← NOT Bit 4
BIT 4,(IY+index) FDCBindex66 Z flag ← NOT Bit 4
BIT 5,A CB6F Z flag ← NOT Bit 5
BIT 5,B CB68 Z flag ← NOT Bit 5
BIT 5,C CB69 Z flag ← NOT Bit 5
BIT 5,D CB6A Z flag ← NOT Bit 5
BIT 5,E CB6B Z flag ← NOT Bit 5
BIT 5,H CB6C Z flag ← NOT Bit 5
BIT 5,L CB6D Z flag ← NOT Bit 5
BIT 5,(HL) CB6E Z flag ← NOT Bit 5
BIT 5,(IX+index) DDCBindex6E Z flag ← NOT Bit 5
BIT 5,(IY+index) FDCBindex6E Z flag ← NOT Bit 5
BIT 6,A CB77 Z flag ← NOT Bit 6
BIT 6,B CB70 Z flag ← NOT Bit 6
BIT 6,C CB71 Z flag ← NOT Bit 6
BIT 6,D CB72 Z flag ← NOT Bit 6
BIT 6,E CB73 Z flag ← NOT Bit 6
BIT 6,H CB74 Z flag ← NOT Bit 6
BIT 6,L CB75 Z flag ← NOT Bit 6
BIT 6,(HL) CB76 Z flag ← NOT Bit 6
BIT 6,(IX+index) DDCBindex76 Z flag ← NOT Bit 6
BIT 6,(IY+index) FDCBindex76 Z flag ← NOT Bit 6
BIT 7,A CB7F Z flag ← NOT Bit 7
BIT 7,B CB78 Z flag ← NOT Bit 7
BIT 7,C CB79 Z flag ← NOT Bit 7
BIT 7,D CB7A Z flag ← NOT Bit 7
BIT 7,E CB7B Z flag ← NOT Bit 7
BIT 7,H CB7C Z flag ← NOT Bit 7
BIT 7,L CB7D Z flag ← NOT Bit 7
BIT 7,(HL) CB7E Z flag ← NOT Bit 7
BIT 7,(IX+index) DDCBindex7E Z flag ← NOT Bit 7
BIT 7,(IY+index) FDCBindex7E Z flag ← NOT Bit 7
RES 0,A CB87 Bit 0 ← 0
RES 0,B CB80 Bit 0 ← 0
RES 0,C CB81 Bit 0 ← 0
RES 0,D CB82 Bit 0 ← 0
RES 0,E CB83 Bit 0 ← 0
RES 0,H CB84 Bit 0 ← 0
RES 0,L CB85 Bit 0 ← 0
RES 0,(HL) CB86 Bit 0 ← 0
RES 0,(IX+index) DDCBindex86 Bit 0 ← 0
RES 0,(IY+index) FDCBindex86 Bit 0 ← 0
RES 1,A CB8F Bit 1 ← 0
RES 1,B CB88 Bit 1 ← 0
RES 1,C CB89 Bit 1 ← 0
RES 1,D CB8A Bit 1 ← 0
RES 1,E CB8B Bit 1 ← 0
RES 1,H CB8C Bit 1 ← 0
RES 1,L CB8D Bit 1 ← 0
RES 1,(HL) CB8E Bit 1 ← 0
RES 1,(IX+index) DDCBindex8E Bit 1 ← 0
RES 1,(IY+index) FDCBindex8E Bit 1 ← 0
RES 2,A CB97 Bit 2 ← 0
RES 2,B CB90 Bit 2 ← 0
RES 2,C CB91 Bit 2 ← 0
RES 2,D CB92 Bit 2 ← 0
RES 2,E CB93 Bit 2 ← 0
RES 2,H CB94 Bit 2 ← 0
RES 2,L CB95 Bit 2 ← 0
RES 2,(HL) CB96 Bit 2 ← 0
RES 2,(IX+index) DDCBindex96 Bit 2 ← 0
RES 2,(IY+index) FDCBindex96 Bit 2 ← 0
RES 3,A CB9F Bit 3 ← 0
RES 3,B CB98 Bit 3 ← 0
RES 3,C CB99 Bit 3 ← 0
RES 3,D CB9A Bit 3 ← 0
RES 3,E CB9B Bit 3 ← 0
RES 3,H CB9C Bit 3 ← 0
RES 3,L CB9D Bit 3 ← 0
RES 3,(HL) CB9E Bit 3 ← 0
RES 3,(IX+index) DDCBindex9E Bit 3 ← 0
RES 3,(IY+index) FDCBindex9E Bit 3 ← 0
RES 4,A CBA7 Bit 4 ← 0
RES 4,B CBA0 Bit 4 ← 0
RES 4,C CBA1 Bit 4 ← 0
RES 4,D CBA2 Bit 4 ← 0
RES 4,E CBA3 Bit 4 ← 0
RES 4,H CBA4 Bit 4 ← 0
RES 4,L CBA5 Bit 4 ← 0
RES 4,(HL) CBA6 Bit 4 ← 0
RES 4,(IX+index) DDCBindexA6 Bit 4 ← 0
RES 4,(IY+index) FDCBindexA6 Bit 4 ← 0
RES 5,A CBAF Bit 5 ← 0
RES 5,B CBA8 Bit 5 ← 0
RES 5,C CBA9 Bit 5 ← 0
RES 5,D CBAA Bit 5 ← 0
RES 5,E CBAB Bit 5 ← 0
RES 5,H CBAC Bit 5 ← 0
RES 5,L CBAD Bit 5 ← 0
RES 5,(HL) CBAE Bit 5 ← 0
RES 5,(IX+index) DDCBindexAE Bit 5 ← 0
RES 5,(IY+index) FDCBindexAE Bit 5 ← 0
RES 6,A CBB7 Bit 6 ← 0
RES 6,B CBB0 Bit 6 ← 0
RES 6,C CBB1 Bit 6 ← 0
RES 6,D CBB2 Bit 6 ← 0
RES 6,E CBB3 Bit 6 ← 0
RES 6,H CBB4 Bit 6 ← 0
RES 6,L CBB5 Bit 6 ← 0
RES 6,(HL) CBB6 Bit 6 ← 0
RES 6,(IX+index) DDCBindexB6 Bit 6 ← 0
RES 6,(IY+index) FDCBindexB6 Bit 6 ← 0
RES 7,A CBBF Bit 7 ← 0
RES 7,B CBB8 Bit 7 ← 0
RES 7,C CBB9 Bit 7 ← 0
RES 7,D CBBA Bit 7 ← 0
RES 7,E CBBB Bit 7 ← 0
RES 7,H CBBC Bit 7 ← 0
RES 7,L CBBD Bit 7 ← 0
RES 7,(HL) CBBE Bit 7 ← 0
RES 7,(IX+index) DDCBindexBE Bit 7 ← 0
RES 7,(IY+index) FDCBindexBE Bit 7 ← 0
SET 0,A CBC7 Bit 0 ← 1
SET 0,B CBC0 Bit 0 ← 1
SET 0,C CBC1 Bit 0 ← 1
SET 0,D CBC2 Bit 0 ← 1
SET 0,E CBC3 Bit 0 ← 1
SET 0,H CBC4 Bit 0 ← 1
SET 0,L CBC5 Bit 0 ← 1
SET 0,(HL) CBC6 Bit 0 ← 1
SET 0,(IX+index) DDCBindexC6 Bit 0 ← 1
SET 0,(IY+index) FDCBindexC6 Bit 0 ← 1
SET 1,A CBCF Bit 1 ← 1
SET 1,B CBC8 Bit 1 ← 1
SET 1,C CBC9 Bit 1 ← 1
SET 1,D CBCA Bit 1 ← 1
SET 1,E CBCB Bit 1 ← 1
SET 1,H CBCC Bit 1 ← 1
SET 1,L CBCD Bit 1 ← 1
SET 1,(HL) CBCE Bit 1 ← 1
SET 1,(IX+index) DDCBindexCE Bit 1 ← 1
SET 1,(IY+index) FDCBindexCE Bit 1 ← 1
SET 2,A CBD7 Bit 2 ← 1
SET 2,B CBD0 Bit 2 ← 1
SET 2,C CBD1 Bit 2 ← 1
SET 2,D CBD2 Bit 2 ← 1
SET 2,E CBD3 Bit 2 ← 1
SET 2,H CBD4 Bit 2 ← 1
SET 2,L CBD5 Bit 2 ← 1
SET 2,(HL) CBD6 Bit 2 ← 1
SET 2,(IX+index) DDCBindexD6 Bit 2 ← 1
SET 2,(IY+index) FDCBindexD6 Bit 2 ← 1
SET 3,A CBDF Bit 3 ← 1
SET 3,B CBD8 Bit 3 ← 1
SET 3,C CBD9 Bit 3 ← 1
SET 3,D CBDA Bit 3 ← 1
SET 3,E CBDB Bit 3 ← 1
SET 3,H CBDC Bit 3 ← 1
SET 3,L CBDD Bit 3 ← 1
SET 3,(HL) CBDE Bit 3 ← 1
SET 3,(IX+index) DDCBindexDE Bit 3 ← 1
SET 3,(IY+index) FDCBindexDE Bit 3 ← 1
SET 4,A CBE7 Bit 4 ← 1
SET 4,B CBE0 Bit 4 ← 1
SET 4,C CBE1 Bit 4 ← 1
SET 4,D CBE2 Bit 4 ← 1
SET 4,E CBE3 Bit 4 ← 1
SET 4,H CBE4 Bit 4 ← 1
SET 4,L CBE5 Bit 4 ← 1
SET 4,(HL) CBE6 Bit 4 ← 1
SET 4,(IX+index) DDCBindexE6 Bit 4 ← 1
SET 4,(IY+index) FDCBindexE6 Bit 4 ← 1
SET 5,A CBEF Bit 5 ← 1
SET 5,B CBE8 Bit 5 ← 1
SET 5,C CBE9 Bit 5 ← 1
SET 5,D CBEA Bit 5 ← 1
SET 5,E CBEB Bit 5 ← 1
SET 5,H CBEC Bit 5 ← 1
SET 5,L CBED Bit 5 ← 1
SET 5,(HL) CBEE Bit 5 ← 1
SET 5,(IX+index) DDCBindexEE Bit 5 ← 1
SET 5,(IY+index) FDCBindexEE Bit 5 ← 1
SET 6,A CBF7 Bit 6 ← 1
SET 6,B CBF0 Bit 6 ← 1
SET 6,C CBF1 Bit 6 ← 1
SET 6,D CBF2 Bit 6 ← 1
SET 6,E CBF3 Bit 6 ← 1
SET 6,H CBF4 Bit 6 ← 1
SET 6,L CBF5 Bit 6 ← 1
SET 6,(HL) CBF6 Bit 6 ← 1
SET 6,(IX+index) DDCBindexF6 Bit 6 ← 1
SET 6,(IY+index) FDCBindexF6 Bit 6 ← 1
SET 7,A CBFF Bit 7 ← 1
SET 7,B CBF8 Bit 7 ← 1
SET 7,C CBF9 Bit 7 ← 1
SET 7,D CBFA Bit 7 ← 1
SET 7,E CBFB Bit 7 ← 1
SET 7,H CBFC Bit 7 ← 1
SET 7,L CBFD Bit 7 ← 1
SET 7,(HL) CBFE Bit 7 ← 1
SET 7,(IX+index) DDCBindexFE Bit 7 ← 1
SET 7,(IY+index) FDCBindexFE Bit 7 ← 1

Bit Shift Instructions
Z80 Mnemonic Machine Code Operation
SLA A CB27
SLA B CB20
SLA C CB21
SLA D CB22
SLA E CB23
SLA H CB24
SLA L CB25
SLA (HL) CB26
SLA (IX+index) DDCBindex26
SLA (IY+index) FDCBindex26
SRA A CB2F
SRA B CB28
SRA C CB29
SRA D CB2A
SRA E CB2B
SRA H CB2C
SRA L CB2D
SRA (HL) CB2E
SRA (IX+index) DDCBindex2E
SRA (IY+index) FDCBindex2E
SLL A CB37
SLL B CB30
SLL C CB31
SLL D CB32
SLL E CB33
SLL H CB34
SLL L CB35
SLL (HL) CB36
SLL (IX+index) DDCBindex36
SLL (IY+index) FDCBindex36
SRL A CB3F
SRL B CB38
SRL C CB39
SRL D CB3A
SRL E CB3B
SRL H CB3C
SRL L CB3D
SRL (HL) CB3E
SRL (IX+index) DDCBindex3E
SRL (IY+index) FDCBindex3E

Numerical order

	          Full Z80 Opcode List Including Undocumented Opcodes
	          ===================================================
	               File: DOCS.Comp.Z80.OpList−Update: 0.10
	                Author: J.G.Harston−Date: 09-09-1997

	nn nn             DD nn          CB nn       FD CB ff nn      ED nn
	--------------------------------------------------------------------------
	00 NOP           −             RLC  B      rlc (iy+0)→b    MOS_QUIT
	01 LD   BC,&0000 −             RLC  C      rlc (iy+0)→c    MOS_CLI
	02 LD   (BC),A   −             RLC  D      rlc (iy+0)→d    MOS_BYTE
	03 INC  BC       −             RLC  E      rlc (iy+0)→e    MOS_WORD
	04 INC  B        −             RLC  H      rlc (iy+0)→h    MOS_WRCH
	05 DEC  B        −             RLC  L      rlc (iy+0)→l    MOS_RDCH
	06 LD   B,&00    −             RLC  (HL)   RLC (IY+0)      MOS_FILE
	07 RLCA          −             RLC  A      rlc (iy+0)→a    MOS_ARGS
	08 EX   AF,AF'   −             RRC  B      rrc (iy+0)→b    MOS_BGET
	09 ADD  HL,BC     ADD  IX,BC     RRC  C      rrc (iy+0)→c    MOS_BPUT
	0A LD   A,(BC)   −             RRC  D      rrc (iy+0)→d    MOS_GBPB
	0B DEC  BC       −             RRC  E      rrc (iy+0)→e    MOS_FIND
	0C INC  C        −             RRC  H      rrc (iy+0)→h    MOS_FF0C
	0D DEC  C        −             RRC  L      rrc (iy+0)→l    MOS_FF0D
	0E LD   C,&00    −             RRC  (HL)   RRC (IY+0)      MOS_FF0E
	0F RRCA          −             RRC  A      rrc (iy+0)→a    MOS_FF0F
	10 DJNZ &4546    −             RL   B      rl  (iy+0)→b    -
	11 LD   DE,&0000 −             RL   C      rl  (iy+0)→c    -
	12 LD   (DE),A   −             RL   D      rl  (iy+0)→d    -
	13 INC  DE       −             RL   E      rl  (iy+0)→e    -
	14 INC  D        −             RL   H      rl  (iy+0)→h    -
	15 DEC  D        −             RL   L      rl  (iy+0)→l    -
	16 LD   D,&00    −             RL   (HL)   RL  (IY+0)      -
	17 RLA           −             RL   A      rl  (iy+0)→a    -
	18 JR   &4546    −             RR   B      rr  (iy+0)→b    -
	19 ADD  HL,DE     ADD  IX,DE     RR   C      rr  (iy+0)→c    -
	1A LD   A,(DE)   −             RR   D      rr  (iy+0)→d    -
	1B DEC  DE       −             RR   E      rr  (iy+0)→e    -
	1C INC  E        −             RR   H      rr  (iy+0)→h    -
	1D DEC  E        −             RR   L      rr  (iy+0)→l    -
	1E LD   E,&00    −             RR   (HL)   RR  (IY+0)      -
	1F RRA           −             RR   A      rr  (iy+0)→a    -
	20 JR   NZ,&4546 −             SLA  B      sla (iy+0)→b    -
	21 LD   HL,&0000  LD   IX,&0000  SLA  C      sla (iy+0)→c    -
	22 LD  (&0000),HL LD  (&0000),IX SLA  D      sla (iy+0)→d    -
	23 INC  HL        INC  IX        SLA  E      sla (iy+0)→e    -
	24 INC  H         INC  IXH       SLA  H      sla (iy+0)→h    -
	25 DEC  H         DEC  IXH       SLA  L      sla (iy+0)→l    -
	26 LD   H,&00     LD   IXH,&00   SLA  (HL)   SLA (IY+0)      -
	27 DAA           −             SLA  A      sla (iy+0)→a    -
	28 JR   Z,&4546  −             SRA  B      sra (iy+0)→b    -
	29 ADD  HL,HL     ADD  IX,IX     SRA  C      sra (iy+0)→c    -
	2A LD  HL,(&0000) LD  IX,(&0000) SRA  D      sra (iy+0)→d    -
	2B DEC  HL        DEC  IX        SRA  E      sra (iy+0)→e    -
	2C INC  L         INC  IXL       SRA  H      sra (iy+0)→h    -
	2D DEC  L         DEC  IXL       SRA  L      sra (iy+0)→l    -
	2E LD   L,&00     LD   IXL,&00   SRA  (HL)   SRA (IY+0)      -
	2F CPL           −             SRA  A      sra (iy+0)→a    -
	30 JR   NC,&4546 −             SLS  B      sls (iy+0)→b    -
	31 LD   SP,&0000 −             SLS  C      sls (iy+0)→c    -
	32 LD   (&0000),A−             SLS  D      sls (iy+0)→d    -
	33 INC  SP       −             SLS  E      sls (iy+0)→e    -
	34 INC  (HL)      INC  (IX+0)    SLS  H      sls (iy+0)→h    -
	35 DEC  (HL)      DEC  (IX+0)    SLS  L      sls (iy+0)→l    -
	36 LD   (HL),&00  LD  (IX+0),&00 SLS  (HL)   SLS (IY+0)      -
	37 SCF           −             SLS  A      sls (iy+0)→a    -
	38 JR   C,&4546  −             SRL  B      srl (iy+0)→b    -
	39 ADD  HL,SP     ADD  IX,SP     SRL  C      srl (iy+0)→c    -
	3A LD   A,(&0000)−             SRL  D      srl (iy+0)→d    -
	3B DEC  SP       −             SRL  E      srl (iy+0)→e    -
	3C INC  A        −             SRL  H      srl (iy+0)→h    -
	3D DEC  A        −             SRL  L      srl (iy+0)→l    -
	3E LD   A,&00    −             SRL  (HL)   SRL (IY+0)      -
	3F CCF           −             SRL  A      srl (iy+0)→a    -
	40 LD   B,B      −             BIT  0,B    bit 0,(iy+0)→b  IN   B,(C)
	41 LD   B,C      −             BIT  0,C    bit 0,(iy+0)→c  OUT  (C),B
	42 LD   B,D      −             BIT  0,D    bit 0,(iy+0)→d  SBC  HL,BC
	43 LD   B,E      −             BIT  0,E    bit 0,(iy+0)→e  LD   (&0000),BC
	44 LD   B,H       LD   B,IXH     BIT  0,H    bit 0,(iy+0)→h  NEG
	45 LD   B,L       LD   B,IXL     BIT  0,L    bit 0,(iy+0)→l  RETN
	46 LD   B,(HL)    LD   B,(IX+0)  BIT  0,(HL) BIT 0,(IY+0)    IM   0
	47 LD   B,A      −             BIT  0,A    bit 0,(iy+0)→a  LD   I,A
	48 LD   C,B      −             BIT  1,B    bit 1,(iy+0)→b  IN   C,(C)
	49 LD   C,C      −             BIT  1,C    bit 1,(iy+0)→c  OUT  (C),C
	4A LD   C,D      −             BIT  1,D    bit 1,(iy+0)→d  ADC  HL,BC
	4B LD   C,E      −             BIT  1,E    bit 1,(iy+0)→e  LD   BC,(&0000)
	4C LD   C,H       LD   C,IXH     BIT  1,H    bit 1,(iy+0)→h  [neg]
	4D LD   C,L       LD   C,IXL     BIT  1,L    bit 1,(iy+0)→l  RETI
	4E LD   C,(HL)    LD   C,(IX+0)  BIT  1,(HL) BIT 1,(IY+0)    [im0]
	4F LD   C,A      −             BIT  1,A    bit 1,(iy+0)→a  LD   R,A
	50 LD   D,B      −             BIT  2,B    bit 2,(iy+0)→b  IN   D,(C)
	51 LD   D,C      −             BIT  2,C    bit 2,(iy+0)→c  OUT  (C),D
	52 LD   D,D      −             BIT  2,D    bit 2,(iy+0)→d  SBC  HL,DE
	53 LD   D,E      −             BIT  2,E    bit 2,(iy+0)→e  LD   (&0000),DE
	54 LD   D,H       LD   D,IXH     BIT  2,H    bit 2,(iy+0)→h  [neg]
	55 LD   D,L       LD   D,IXL     BIT  2,L    bit 2,(iy+0)→l  [retn]
	56 LD   D,(HL)    LD   D,(IX+0)  BIT  2,(HL) BIT 2,(IY+0)    IM   1
	57 LD   D,A      −             BIT  2,A    bit 2,(iy+0)→a  LD   A,I
	58 LD   E,B      −             BIT  3,B    bit 3,(iy+0)→b  IN   E,(C)
	59 LD   E,C      −             BIT  3,C    bit 3,(iy+0)→c  OUT  (C),E
	5A LD   E,D      −             BIT  3,D    bit 3,(iy+0)→d  ADC  HL,DE
	5B LD   E,E      −             BIT  3,E    bit 3,(iy+0)→e  LD   DE,(&0000)
	5C LD   E,H       LD   E,IXH     BIT  3,H    bit 3,(iy+0)→h  [neg]
	5D LD   E,L       LD   E,IXL     BIT  3,L    bit 3,(iy+0)→l  [reti]
	5E LD   E,(HL)    LD   E,(IX+0)  BIT  3,(HL) BIT 3,(IY+0)    IM   2
	5F LD   E,A      −             BIT  3,A    bit 3,(iy+0)→a  LD   A,R
	60 LD   H,B       LD   IXH,B     BIT  4,B    bit 4,(iy+0)→b  IN   H,(C)
	61 LD   H,C       LD   IXH,C     BIT  4,C    bit 4,(iy+0)→c  OUT  (C),H
	62 LD   H,D       LD   IXH,D     BIT  4,D    bit 4,(iy+0)→d  SBC  HL,HL
	63 LD   H,E       LD   IXH,E     BIT  4,E    bit 4,(iy+0)→e  LD   (&0000),HL
	64 LD   H,H       LD   IXH,IXH   BIT  4,H    bit 4,(iy+0)→h  [neg]
	65 LD   H,L       LD   IXH,IXL   BIT  4,L    bit 4,(iy+0)→l  [retn]
	66 LD   H,(HL)    LD   H,(IX+0)  BIT  4,(HL) BIT 4,(IY+0)    [im0]
	67 LD   H,A       LD   IXH,A     BIT  4,A    bit 4,(iy+0)→a  RRD
	68 LD   L,B       LD   IXL,B     BIT  5,B    bit 5,(iy+0)→b  IN   L,(C)
	69 LD   L,C       LD   IXL,C     BIT  5,C    bit 5,(iy+0)→c  OUT  (C),L
	6A LD   L,D       LD   IXL,D     BIT  5,D    bit 5,(iy+0)→d  ADC  HL,HL
	6B LD   L,E       LD   IXL,E     BIT  5,E    bit 5,(iy+0)→e  LD   HL,(&0000)
	6C LD   L,H       LD   IXL,IXH   BIT  5,H    bit 5,(iy+0)→h  [neg]
	6D LD   L,L       LD   IXL,IXL   BIT  5,L    bit 5,(iy+0)→l  [reti]
	6E LD   L,(HL)    LD   L,(IX+0)  BIT  5,(HL) BIT 5,(IY+0)    [im0]
	6F LD   L,A       LD   IXL,A     BIT  5,A    bit 5,(iy+0)→a  RLD
	70 LD   (HL),B    LD   (IX+0),B  BIT  6,B    bit 6,(iy+0)→b  IN   F,(C)
	71 LD   (HL),C    LD   (IX+0),C  BIT  6,C    bit 6,(iy+0)→c  OUT  (C),F
	72 LD   (HL),D    LD   (IX+0),D  BIT  6,D    bit 6,(iy+0)→d  SBC  HL,SP
	73 LD   (HL),E    LD   (IX+0),E  BIT  6,E    bit 6,(iy+0)→e  LD   (&0000),SP
	74 LD   (HL),H    LD   (IX+0),H  BIT  6,H    bit 6,(iy+0)→h  [neg]
	75 LD   (HL),L    LD   (IX+0),L  BIT  6,L    bit 6,(iy+0)→l  [retn]
	76 HALT          −             BIT  6,(HL) BIT 6,(IY+0)    [im1]
	77 LD   (HL),A    LD   (IX+0),A  BIT  6,A    bit 6,(iy+0)→a  [ld i,i?]
	78 LD   A,B      −             BIT  7,B    bit 7,(iy+0)→b  IN   A,(C)
	79 LD   A,C      −             BIT  7,C    bit 7,(iy+0)→c  OUT  (C),A
	7A LD   A,D      −             BIT  7,D    bit 7,(iy+0)→d  ADC  HL,SP
	7B LD   A,E      −             BIT  7,E    bit 7,(iy+0)→e  LD   SP,(&0000)
	7C LD   A,H       LD   A,IXH     BIT  7,H    bit 7,(iy+0)→h  [neg]
	7D LD   A,L       LD   A,IXL     BIT  7,L    bit 7,(iy+0)→l  [reti]
	7E LD   A,(HL)    LD   A,(IX+0)  BIT  7,(HL) BIT 7,(IY+0)    [im2]
	7F LD   A,A      −             BIT  7,A    bit 7,(iy+0)→a  [ld r,r?]
	80 ADD  A,B      −             RES  0,B    res 0,(iy+0)→b  -
	81 ADD  A,C      −             RES  0,C    res 0,(iy+0)→c  -
	82 ADD  A,D      −             RES  0,D    res 0,(iy+0)→d  -
	83 ADD  A,E      −             RES  0,E    res 0,(iy+0)→e  -
	84 ADD  A,H       ADD  A,IXH     RES  0,H    res 0,(iy+0)→h  -
	85 ADD  A,L       ADD  A,IXL     RES  0,L    res 0,(iy+0)→l  -
	86 ADD  A,(HL)    ADD  A,(IX+0)  RES  0,(HL) RES 0,(IY+0)    -
	87 ADD  A,A      −             RES  0,A    res 0,(iy+0)→a  -
	88 ADC  A,B      −             RES  1,B    res 1,(iy+0)→b  -
	89 ADC  A,C      −             RES  1,C    res 1,(iy+0)→c  -
	8A ADC  A,D      −             RES  1,D    res 1,(iy+0)→d  -
	8B ADC  A,E      −             RES  1,E    res 1,(iy+0)→e  -
	8C ADC  A,H       ADC  A,IXH     RES  1,H    res 1,(iy+0)→h  -
	8D ADC  A,L       ADC  A,IXL     RES  1,L    res 1,(iy+0)→l  -
	8E ADC  A,(HL)    ADC  A,(IX+0)  RES  1,(HL) RES 1,(IY+0)    -
	8F ADC  A,A      −             RES  1,A    res 1,(iy+0)→a  -
	90 SUB  A,B      −             RES  2,B    res 2,(iy+0)→b  -
	91 SUB  A,C      −             RES  2,C    res 2,(iy+0)→c  -
	92 SUB  A,D      −             RES  2,D    res 2,(iy+0)→d  -
	93 SUB  A,E      −             RES  2,E    res 2,(iy+0)→e  -
	94 SUB  A,H       SUB  A,IXH     RES  2,H    res 2,(iy+0)→h  -
	95 SUB  A,L       SUB  A,IXL     RES  2,L    res 2,(iy+0)→l  -
	96 SUB  A,(HL)    SUB  A,(IX+0)  RES  2,(HL) RES 2,(IY+0)    -
	97 SUB  A,A      −             RES  2,A    res 2,(iy+0)→a  -
	98 SBC  A,B      −             RES  3,B    res 3,(iy+0)→b  -
	99 SBC  A,C      −             RES  3,C    res 3,(iy+0)→c  -
	9A SBC  A,D      −             RES  3,D    res 3,(iy+0)→d  -
	9B SBC  A,E      −             RES  3,E    res 3,(iy+0)→e  -
	9C SBC  A,H       SBC  A,IXH     RES  3,H    res 3,(iy+0)→h  -
	9D SBC  A,L       SBC  A,IXL     RES  3,L    res 3,(iy+0)→l  -
	9E SBC  A,(HL)    SBC  A,(IX+0)  RES  3,(HL) RES 3,(IY+0)    -
	9F SBC  A,A      −             RES  3,A    res 3,(iy+0)→a  -
	A0 AND  B        −             RES  4,B    res 4,(iy+0)→b  LDI
	A1 AND  C        −             RES  4,C    res 4,(iy+0)→c  CPI
	A2 AND  D        −             RES  4,D    res 4,(iy+0)→d  INI
	A3 AND  E        −             RES  4,E    res 4,(iy+0)→e  OTI
	A4 AND  H         AND  IXH       RES  4,H    res 4,(iy+0)→h  -
	A5 AND  L         AND  IXL       RES  4,L    res 4,(iy+0)→l  -
	A6 AND  (HL)      AND  (IX+0)    RES  4,(HL) RES 4,(IY+0)    -
	A7 AND  A        −             RES  4,A    res 4,(iy+0)→a  -
	A8 XOR  B        −             RES  5,B    res 5,(iy+0)→b  LDD
	A9 XOR  C        −             RES  5,C    res 5,(iy+0)→c  CPD
	AA XOR  D        −             RES  5,D    res 5,(iy+0)→d  IND
	AB XOR  E        −             RES  5,E    res 5,(iy+0)→e  OTD
	AC XOR  H         XOR  IXH       RES  5,H    res 5,(iy+0)→h  -
	AD XOR  L         XOR  IXL       RES  5,L    res 5,(iy+0)→l  -
	AE XOR  (HL)      XOR  (IX+0)    RES  5,(HL) RES 5,(IY+0)    -
	AF XOR  A        −             RES  5,A    res 5,(iy+0)→a  -
	B0 OR   B        −             RES  6,B    res 6,(iy+0)→b  LDIR
	B1 OR   C        −             RES  6,C    res 6,(iy+0)→c  CPIR
	B2 OR   D        −             RES  6,D    res 6,(iy+0)→d  INIR
	B3 OR   E        −             RES  6,E    res 6,(iy+0)→e  OTIR
	B4 OR   H         OR   IXH       RES  6,H    res 6,(iy+0)→h  -
	B5 OR   L         OR   IXL       RES  6,L    res 6,(iy+0)→l  -
	B6 OR   (HL)      OR   (IX+0)    RES  6,(HL) RES 6,(IY+0)    -
	B7 OR   A        −             RES  6,A    res 6,(iy+0)→a  -
	B8 CP   B        −             RES  7,B    res 7,(iy+0)→b  LDDR
	B9 CP   C        −             RES  7,C    res 7,(iy+0)→c  CPDR
	BA CP   D        −             RES  7,D    res 7,(iy+0)→d  INDR
	BB CP   E        −             RES  7,E    res 7,(iy+0)→e  OTDR
	BC CP   H         CP   IXH       RES  7,H    res 7,(iy+0)→h  -
	BD CP   L         CP   IXL       RES  7,L    res 7,(iy+0)→l  -
	BE CP   (HL)      CP   (IX+0)    RES  7,(HL) RES 7,(IY+0)    -
	BF CP   A        −             RES  7,A    res 7,(iy+0)→a  -
	C0 RET  NZ       −             SET  0,B    set 0,(iy+0)→b  -
	C1 POP  BC       −             SET  0,C    set 0,(iy+0)→c  -
	C2 JP   NZ,&0000 −             SET  0,D    set 0,(iy+0)→d  -
	C3 JP   &0000    −             SET  0,E    set 0,(iy+0)→e  -
	C4 CALL NZ,&0000 −             SET  0,H    set 0,(iy+0)→h  -
	C5 PUSH BC       −             SET  0,L    set 0,(iy+0)→l  -
	C6 ADD  A,&00    −             SET  0,(HL) SET 0,(IY+0)    -
	C7 RST  &00      −             SET  0,A    set 0,(iy+0)→a  -
	C8 RET  Z        −             SET  1,B    set 1,(iy+0)→b  -
	C9 RET           −             SET  1,C    set 1,(iy+0)→c  -
	CA JP   Z,&0000  −             SET  1,D    set 1,(iy+0)→d  -
	CB **** CB ****  −             SET  1,E    set 1,(iy+0)→e  -
	CC CALL Z,&0000  −             SET  1,H    set 1,(iy+0)→h  -
	CD CALL &0000    −             SET  1,L    set 1,(iy+0)→l  -
	CE ADC  A,&00    −             SET  1,(HL) SET 1,(IY+0)    -
	CF RST  &08      −             SET  1,A    set 1,(iy+0)→a  -
	D0 RET  NC       −             SET  2,B    set 2,(iy+0)→b  -
	D1 POP  DE       −             SET  2,C    set 2,(iy+0)→c  -
	D2 JP   NC,&0000 −             SET  2,D    set 2,(iy+0)→d  -
	D3 OUT  (&00),A  −             SET  2,E    set 2,(iy+0)→e  -
	D4 CALL NC,&0000 −             SET  2,H    set 2,(iy+0)→h  -
	D5 PUSH DE       −             SET  2,L    set 2,(iy+0)→l  -
	D6 SUB  A,&00    −             SET  2,(HL) SET 2,(IY+0)    -
	D7 RST  &10      −             SET  2,A    set 2,(iy+0)→a  -
	D8 RET  C        −             SET  3,B    set 3,(iy+0)→b  -
	D9 EXX           −             SET  3,C    set 3,(iy+0)→c  -
	DA JP   C,&0000  −             SET  3,D    set 3,(iy+0)→d  -
	DB IN   A,(&00)  −             SET  3,E    set 3,(iy+0)→e  -
	DC CALL C,&0000  −             SET  3,H    set 3,(iy+0)→h  -
	DD **** DD ****  −             SET  3,L    set 3,(iy+0)→l  -
	DE SBC  A,&00    −             SET  3,(HL) SET 3,(IY+0)    -
	DF RST  &18      −             SET  3,A    set 3,(iy+0)→a  -
	E0 RET  PO       −             SET  4,B    set 4,(iy+0)→b  -
	E1 POP  HL        POP  IX        SET  4,C    set 4,(iy+0)→c  -
	E2 JP   PO,&0000 −             SET  4,D    set 4,(iy+0)→d  -
	E3 EX   (SP),HL   EX   (SP),IX   SET  4,E    set 4,(iy+0)→e  -
	E4 CALL PO,&0000 −             SET  4,H    set 4,(iy+0)→h  -
	E5 PUSH HL        PUSH IX        SET  4,L    set 4,(iy+0)→l  -
	E6 AND  &00      −             SET  4,(HL) SET 4,(IY+0)    -
	E7 RST  &20      −             SET  4,A    set 4,(iy+0)→a  -
	E8 RET  PE       −             SET  5,B    set 5,(iy+0)→b  -
	E9 JP   (HL)      JP   (IX)      SET  5,C    set 5,(iy+0)→c  -
	EA JP   PE,&0000 −             SET  5,D    set 5,(iy+0)→d  -
	EB EX   DE,HL    −             SET  5,E    set 5,(iy+0)→e  -
	EC CALL PE,&0000 −             SET  5,H    set 5,(iy+0)→h  -
	ED **** ED ****  −             SET  5,L    set 5,(iy+0)→l  -
	EE XOR  &00      −             SET  5,(HL) SET 5,(IY+0)    -
	EF RST  &28      −             SET  5,A    set 5,(iy+0)→a  -
	F0 RET  P        −             SET  6,B    set 6,(iy+0)→b  -
	F1 POP  AF       −             SET  6,C    set 6,(iy+0)→c  -
	F2 JP   P,&0000  −             SET  6,D    set 6,(iy+0)→d  -
	F3 DI            −             SET  6,E    set 6,(iy+0)→e  -
	F4 CALL P,&0000  −             SET  6,H    set 6,(iy+0)→h  -
	F5 PUSH AF       −             SET  6,L    set 6,(iy+0)→l  -
	F6 OR   &00      −             SET  6,(HL) SET 6,(IY+0)    -
	F7 RST  &30      −             SET  6,A    set 6,(iy+0)→a  -
	F8 RET  M        −             SET  7,B    set 7,(iy+0)→b  [z80]
	F9 LD   SP,HL    −             SET  7,C    set 7,(iy+0)→c  [z80]
	FA JP   M,&0000  −             SET  7,D    set 7,(iy+0)→d  [z80]
	FB EI            −             SET  7,E    set 7,(iy+0)→e  ED_LOAD
	FC CALL M,&0000  −             SET  7,H    set 7,(iy+0)→h  [z80]
	FD **** FD ****  −             SET  7,L    set 7,(iy+0)→l  [z80]
	FE CP   &00      −             SET  7,(HL) SET 7,(IY+0)    [z80]
	FF RST  &38      −             SET  7,A    set 7,(iy+0)→a  ED_DOS

	Notes on index registers
	------------------------
	Where DD and IX are mentioned, FD and IY may be substituted and vis versa.

	Notes on Indexed Shift/Bit Operations
	-------------------------------------
	A shift or bit operation on an indexed byte in memory is done by prefixing
	a CB opcode refering to (HL) with DD or FD to specify (IX+n) or (IY+n).
	If the CB opcode does not refer to (HL), slightly differing things happen.
	The majority of Z80 CPUs execute them as shown; the shift or bit operation
	is done on and indexed byte in memory, and then if the opcode does not
	specify (HL) originally, the resultant byte is copied into the specified
	register.  This is summarised with this example:
	       CB 0x    RLC r          FD CB nn 0x     RLC (IY+nn)→r
	       for x=0..5, 7 for r=B,C,D,E,H,L,A

	Some CPUs allow access to the high and low halves of the index register,
	if x is 4 or 5, the operation does RLC IYH or RLC IYH.
	       CB 04   RLC H           FD CB nn 04     RLC IYH
	       CB 05   RLC L           FD CB nn 05     RLC IYL

	Some CPUs treat all the subcodes as accessing the indexed byte and nothing
	else:
	       CB 0x   RLC r           FD CB nn 0X     RLC (IY+nn)
	                               for all x=0..7

	Notes on ED opcodes
	-------------------
	J.G.Harston's !Z80Tube Z80 CoPro emulator includes the extra opcodes ED00
	to ED0F to interface with the host.  G.A.Lunter's Z80 Spectrum emulator
	includes the extra opcodes EDF8 to EDFF to interface to the host.

ASCII codes


ASCII

Hex

Symbol

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

NUL
SOH
STX
ETX
EOT
ENQ
ACK
BEL
BS
TAB
LF
VT
FF
CR
SO
SI


ASCII

Hex

Symbol

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F

DLE
DC1
DC2
DC3
DC4
NAK
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US


ASCII

Hex

Symbol

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F

(space)
!
"
#
$
%
&
'
(
)
*
+
,
-
.
/


ASCII

Hex

Symbol

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

0
1
2
3
4
5
6
7
8
9
:
;
<
=
>
?


ASCII

Hex

Symbol

64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F

@
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O


ASCII

Hex

Symbol

80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95

50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F

P
Q
R
S
T
U
V
W
X
Y
Z
[
\
]
^
_


ASCII

Hex

Symbol

96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111

60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F

`
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o


ASCII

Hex

Symbol

112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F

p
q
r
s
t
u
v
w
x
y
z
{
|
}
~



Code Snippets and Optimisations

Code replacements

xor a vs. ld a,0

A simple way to set a to zero, saving 1 byte and 3 T-states. Don't use this if you want to preserve flags.

or a vs. cp 0

If you want to compare for equality, sign or parity, you can save 1 byte and 3 T-states. Also always resets C flag.

dec a vs. cp 1

If you can, dec a is a smaller and faster way to check if a or any other register is 1. 8-bit increments and decrements will effect both the z flag and sign flag, among other things.

inc a vs. cp 255

Again, this is a byte smaller and 3 t-states faster if you use inc a. It does not preserve a, but you can often do this and it works on all of the main 8-bit registers and (hl).

adc a,0 vs. jr nc,$+3 \ inc a

adc a,0 is 7 t-states and 2 bytes, whereas the latter is 3 bytes and 11 t-states if the c flag is set, 12 if it is reset. Save a byte and 4 to 5 cycles !

ccf \ adc a,0 vs. jr c,$+3 \ inc a

They are the same size, but the former is always 11 t-states whereas the latter is either 11 or 12 depending on the c flag.

sbc a,0 vs. jr nc,$+3 \ dec a

See adc a,0 vs. jr nc,$+3 \ inc a.

ccf \ sbc a,0 vs. jr c,$+3 \ dec a

See ccf \ adc a,0 vs. jr c,$+3 \ inc a.

scf \ ccf

This is used to reset the c flag, but there are many other ways to do that. This is 8 t-states, 2 bytes, but the following are 1 byte, 4 t-states:

	or a     ;c flag reset, z flag is set if A = 0
	and a   ;c flag reset, z flag is set if A=0
	xor a   ;c flag reset, always sets the z flag, sets A=0
	cp a    ;c flag reset, always sets the z flag
	or 1    ;c flag reset, z flag reset, alters A
	or 80h  ;c flag reset, z flag reset, set sign flag negative, alters A
	xor a   ;c flag reset, z flag set, set sign flag positive, sets A = 0
	sub a   ;c flag reset, always sets the z flag, sets A=0
	

As well, the following are two bytes, but 7 t-states. You should not use these :
	sub 0
	add a,0
	cp 0
	

In each of these cases, other flags are also modified.

Comparison

Doing a "cp n", sets the flags according to the subtraction "a−n" as follows:
	cp n
	jr z,equal              ; n == a
	jr c,greater_or_equal   ; n >= a
	jr nc,less_than         ; n < a
	jr nz,not_equal         ; n != a
	

Z80 Flag Affection

The flag register has the following structure:
Bit 7 6 5 4 3 2 1 0
Flag S Z H P/V N C
The flags are set according to the result of the last instruction. The standard behaviour is:
S−Sign flag
Set if the 2-complement value is negative (copy of MSB)
Z−Zero flag
Set if the value is zero
H−Half Carry
Carry from bit 3 to bit 4
P/V−Parity or Overflow
Parity set if even number of bits set
Overflow set if the 2-complement result does not fit in the register
N−Subtract
Set if the last operation was a subtraction
C−Carry
Set if the result did not fit in the register
The following table contains all the instructions that affect the F register.

Key:

InstructionFlagsNotes
ADD/ADC/SUB/SBCSZ-H-VNC
CP rSZ-H-VNCCP is just SUB with the result thrown away
INC/DEC rSZ-H-VN-
16 bit additions are done in two steps: first the two lower bytes are added, the two higher bytes.
ADD s---*--0CH from higher bytes addition
ADC/SBC sSZ0-*-VNCH from higher bytes addition
AND rSZ-1-P00
OR/XOR rSZ-0-P00
RLCA/RLA/RRCA/RRA---0--0C
RLC/RL/RRC/RR rSZ-0-P0C
SLA/SLL/SRA/SRL rSZ-0-P0CSLL is like SLA except b0 gets set
RRD/RLDSZ-0-P0-Flags set on result in A
BIT n,r*Z-1-*0-PV as Z, S set only if n=7 and b7 of r set. Behaves much like AND r,2^n
CCF---*--0*C=1-C, H as old C
SCF---0--01
CPL---1--1-
NEGSZ-H-V1CA=0-A (Zaks gets C wrong)
DAASZ-*-P-*H from internal correction, C for cascade BCD
LD A,R/LD A,ISZ-0-*0-PV as IFF2
LDI/LDIR/LDD/LDIR---0-*0-PV set if BC not 0
CPI/CPIR/CPD/CPDRSZ-H-*1-PV set if BC not 0. S,Z,H from (A−(HL)) as in CP (HL)
IN r,(C)SZ-0-P0-Also true for IN F,(C)
INI/INIR/IND/INDRSZ-?-???Flags affected as in DEC B
OUTI/OTIR/OUTD/OTDRSZ-?-???Flags affected as in DEC B
All others--------Except for POP AF and EX AF,AF', of course...

Optimised Code Snippets

For any 8-bit register, you can use the following:

	inc [reg8]
	dec [reg8]
	

This will set the z flag if the register is 0, else nz. It is 8 t-states, 2 bytes, and preserves registers.

Set A=0

ld a,0 is 2 bytes, 7 t-states, the following are 1-byte and 4 t-states:

	xor a
	sub a
	

Note that these will change flags, but usually that is okay.

16-bit CP

To compare HL to another 16-bit register, you can do the following:

	or a
	sbc hl,[reg16]
	add hl,[reg16]
	

The or a is simply to reset the c flag, so if the c flag is reset at this point, don't include that and save a byte plus 4 t-states. The speed here is 4+15+11 = 30 t-states and it is 4 bytes total.

Conditionally Set or Reset A

In some cases, you need to set all of the bits in A or reset all of them based on a flag. If you are using the c flag:

	sbc a,a
	

1 byte, 4 t-states is all it takes. It also preserves the c flag, so if the c flag was set, it sets A=255, else A=0 and the c flag stays the same.

16-bit NEG

To get the negative (additive inverse) of a 16-bit register, the following 6 byte, 24 t-state routine can be used:

	xor a
	sub [LSBreg16]
	ld [LSBreg16],a
	sbc a,a
	sub [MSBreg16]
	ld [MSBreg16],a
	

An example code would be:
	xor a
	sub l
	ld l,a
	sbc a,a
	sub h
	ld h,a
	

ld hl,(hl)

Often we want to use indirection when using a lookup table of addresses. For example, say you have a look-up table for strings:

	LUT:
	.dw String1
	.dw String2
	.dw String3
	.dw String4

	String1: .db "String1",0
	String2: .db "String2",0
	String3: .db "String3",0
	String4: .db "String4",0
	

And say you wanted to store the location of the string in HL. Assuming HL already points to the address located in the LUT:
	ld e,(hl)
	inc hl
	ld d,(hl)
	ex de,hl
	

That is 4 bytes, 24 t-states, but it destroys DE. The following is the same size and speed, destroying A:
	ld a,(hl)
	inc hl
	ld h,(hl)
	ld l,a